Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - ram verilog

Search list

[Other Embeded program] ReadHexFile

Description: 将16进制文件转换成RAM可读的文件,verilog语言编写-229 to 16 documents into RAM readable document, verilog language
Platform: | Size: 1024 | Author: 彭琦 | Hits:

[MPI] sdram_verilog_lattice

Description: 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度就可以了.-FPGA has been successfully controlled by SDRAM controller code. As long as you need to modify the width of it.
Platform: | Size: 187392 | Author: chen qiming | Hits:

[VHDL-FPGA-Verilog] rom

Description: Read-only memory,Verilog code
Platform: | Size: 8192 | Author: leigh lee | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: | Size: 62464 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] Verilog_FIFO_ram

Description: 一个可以综合的Verilog 写的FIFO存储器，word格式-An integrated Verilog wrote FIFO memory, word format
Platform: | Size: 19456 | Author: hjx | Hits:

[VHDL-FPGA-Verilog] FPGA_two-way_IO

Description: FPGA Verilog,双向端口的研究,比较全,由ASSIGN和ALWAYS模块组成,测试可用-FPGA Verilog, bi-directional port studies comparing full-, and ALWAYS by ASSIGN modules, testing available
Platform: | Size: 115712 | Author: 鲍纯贝 | Hits:

[VHDL-FPGA-Verilog] T4_sdram_control

Description: verilog语言 利用FPGA控制SDRAM，相信很多朋友都需要 快下载吧-control FPGA Verilog language use SDRAM, believe that many of my friends need to download it faster
Platform: | Size: 19456 | Author: 杜菲 | Hits:

[VHDL-FPGA-Verilog] 8051-Verilog

Description: 使用CPLD仿真8051核,内有源程序和说明,来之不易-CPLD simulation using 8051 nuclear, which has source code and description, the hard-won
Platform: | Size: 90112 | Author: 梁志洪 | Hits:

[OS Develop] FIFO

Description: fifo.v verilog实现的先进先出存储器-fifo.vverilog realize the FIFO memory
Platform: | Size: 2048 | Author: patrick | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[SCM] ProfiBus_Modbus_2008

Description: SPC3 PROGRAMS SP C3 PROGRAMS
Platform: | Size: 5120 | Author: ZHUWEIBING | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束，可以重新设定SEL的值选择下一个通道。模块数据线为8位，显示器件为4个8段LED。 7.数据采集模式如下：单通道采集（由SEL信号选择通道），多通道顺次采集（当前通道采满后转入下一通道），多通道并行采集（每通道依次采集一个数据）。模式由控制信号MODE选择，采集数据的总个数由NUM_COLLECT给出。 8.数据采集过程中不能读取，数据读取过程中不能采集-err
Platform: | Size: 5782528 | Author: pengfu | Hits:

[VHDL-FPGA-Verilog] profiles

Description: source code of counter,ram,lfsr etc
Platform: | Size: 2048 | Author: narsimha | Hits:

[Other Embeded program] ShiftRegister

Description: Shift register verilog code
Platform: | Size: 1024 | Author: selcuk | Hits:

[VHDL-FPGA-Verilog] dual_port_ram

Description: 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
Platform: | Size: 274432 | Author: zhangyan | Hits:

[VHDL-FPGA-Verilog] miffile

Description: 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Platform: | Size: 1024 | Author: 何亮 | Hits:

[VHDL-FPGA-Verilog] hh

Description: 双口RAM的verilog描述 双口RAM的verilog描述-Dual-port RAM of the verilog description of dual-port RAM of the verilog description
Platform: | Size: 7168 | Author: 落木 | Hits:

[VHDL-FPGA-Verilog] HardCamera

Description: The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable
Platform: | Size: 5120 | Author: Joelmir J Lopes | Hits:

[Other] ADV7123_a

Description: adv7123 ram dac 10bit used always for hicolor fpga designs also soc systems
Platform: | Size: 309248 | Author: urga turg | Hits:

[VHDL-FPGA-Verilog] ZBTSRAM

Description: 高速同步SRAM控制器参考设计VHDL代码-High-speed synchronous SRAM controller reference design VHDL code
Platform: | Size: 8192 | Author: wang | Hits:
« 1 2 3 4 56 7 8 9 10 11 »

CodeBus www.codebus.net